[flash_ctrl] Enable firmware dealing with multi-bit ECC and ICV errors #22431
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@matutem I've triggered a full DV regression locally and will report back once I have the results. |
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The results are here: |
Before, these two errors types led to a fatal alert which is problematic during firmware selection and verification. This commit changes the design in the following way: - The two relevant bits in the FAULT_STATUS CSR are made clearable by software. Other bits in this register remain sticky. - The corresponding alert is no longer fatal. This means the alert is only sent out until the two bits are cleared by software. To be on the safe side, firmware can still classify the alert as fatal on the receiver side (in the alert handler). For the other error sources, the alert keeps getting triggered as before, i.e., it remains fatal. For more background information, refer to lowRISC#21353. This resolves lowRISC#21637. Signed-off-by: Pirmin Vogel <[email protected]>
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Before, these two errors types led to a fatal alert which is problematic during firmware selection and verification. This commit changes the design in the following way:
This means the alert is only sent out until the two bits are cleared by software. To be on the safe side, firmware can still classify the alert as fatal on the receiver side (in the alert handler). For the other error sources, the alert keeps getting triggered as before, i.e., it remains fatal.
For more background information, refer to #21353.
This resolves #21637.